Final Report Summary - PERSEUS (3D modelling of the performance and variability of high electron mobility transistors for future digital applications)
CMOS Si technology experienced a revolutionary change with the introduction of a hafnium based high-κ dielectric and a metal gate by Intel at the 45 nm technology. An additional dramatic change in device architecture occurred at the 22 nm technology at which a 3D Tri-Gate architecture was firstly used in mass production by Intel. Intensive academic and industry research demonstrated that beyond the 16 nm CMOS technology devices based on silicon channels might not be able to deliver the on-current prescribed by the International Technology Roadmap for Semiconductors (ITRS) and dictated by the circuit design. To move forward, radical changes need to be introduced into materials base of the CMOS devices. Replacing single-gate transistors with multiple-gate ones provides a better control over the channel transport. However, all these expensive changes may not be enough and a replacement of Si in the channel by high mobility materials may be necessary in order to achieve a desired performance for a particular digital application. On the other hand, the increasing variability in the device characteristics is among major challenges for the scaling and integration for present and next generation of devices and circuits.
During the Perseus project, we investigated the performance and scalability of Si and In0.53Ga0.47As silicon/InGaAs-on-insulator vertical fin field effect transistors (SOI FinFETs) using state-of-the-art in-house-built 3D simulation tools: i) drift-diffusion, ii) Monte Carlo (MC) and iii) Non-Equilibrium Green's Function (NEGF) techniques. Three different technological nodes were analysed, with gate lengths of 14.0 12.8 and 10.4 nm for the InGaAs FinFETs and 12.8 10.7 and 8.1 nm for the Si devices. All the device dimensions were designed to meet the 2012 ITRS targets for high-performance logic multi-gate devices. At a high drain bias (0.6 V - 0.7 V), for the Si FinFET, the scaling from the 12.8 nm to 10.7 and 8.1 nm gate lengths increased the on current 25% and 64%, respectively. For the InGaAs FinFET, the increases were 5% and 44% when scaled from 14.0 nm to 12.8 and 10.4 nm gate lengths. Comparing both technologies, the 12.8 and 10.4 nm InGaAs FinFETs delivered 27% and 33% larger on-currents than the 12.8 and 10.7 nm Si FinFETs. The ION/IOFF ratio for the InGaAs FinFETs (9.5-6.6x104) was slightly better than for the Si devices (5.9-6.1x104). The more pronounced S/D tunnelling affecting the InGaAs FinFETs leads to a larger deterioration in their sub-threshold slope (less than 10%) and DIBL (around 20%) when compared to the equivalent gate length Si devices.
Another important part of the project was to study microscopic sources of fluctuations affecting Si and III-V FinFETs. Initially, we studied the impact that three different sources of variability had on the performance of a 14 nm gate length In0.53Ga0.47As FinFET. Low (0.05 V) and high (0.6 V – 0.7 V) drain biases studies were carried out analysing: i) the presence of random dopants in both the channel and the source and drain regions, ii) the line-edge roughness, characterized by the root mean square height (RMS) and the correlation length (CL) and iii) the metal-gate work function variations characterized by the grain size (GS). The study of each source of variability required the simulation of 300 microscopically different transistors. These studies were performed with a 3D parallel finite-element drift-diffusion device simulator that incorporated quantum corrections via a finite-element density gradient approach. The random-dopant induced threshold-voltage (VT) variations (σ VT = 6mV) were similar to those observed in SOI FinFETs. The line-edge roughness induced VT variations (σ VT < 6mV) were similar to the random-dopant ones when RMS=1, and smaller to those observed in SOI FinFETs (around 18 mV). For larger RMS values, the line-edge roughness variability exhibited σ VT ranging from 11 mV, when CL= 10nm and RMS = 2nm, to 19 mV, when CL= 20nm and RMS = 3nm. The metal gate work-function variations were the dominant source of variability in the sub-threshold characteristics. Taking into account that the metal used in the gate was WN, the σ VT ranged from 106 mV when GS = 10 nm to 43 mV when GS = 3 nm, which was larger than the values observed in equivalent TiN metal-gate Si FinFETs.
We also studied and compared the line-edge roughness and TiN metal grain work-function induced variability affecting off and on device characteristics of an In0.53Ga0.47As FinFET with a gate length of 10.4 nm and a Si FinFET with a gate length of 10.7 nm. We analysed the impact of the variability by assessing five figures of merit: threshold voltage (VT), Sub-threshold slope (SS), off-current (IOFF), drain-induced-barrier-lowering (DIBL) and on-current (ION). For this particular study, we have used 3D finite-element quantum-corrected drift-diffusion simulations were employed for variability studies in the sub-threshold region while, in the on-region, we used 3D finite-element quantum-corrected ensemble Monte Carlo simulations. We observed that the In0.53Ga0.47As FinFET was more resilient to the line-edge roughness and metal grain work-function variability in the sub-threshold compared to the Si FinFET due to the stronger carrier confinement present in the In0.53Ga0.47As channel. However, the on-current variability due to line-edge roughness was between 2-3 times larger for the InGaAs FinFET than for the Si device. The on-current variability due to metal gate work-function fluctuations was around 4 times larger for the InGaAs FinFET than for the Si device. For the Si FinFET, both sources of variability had a similar impact on the on-current. However, for the InGaAs FinFET, the on-current metal gate work-function variability was generally much larger than the observed due to line-edge roughness.
The kind of scaling and variability studies performed in the Perseus project for Si and III-V nano-scaled FinEFTs are vital for the proper assessment of their scaling potential. The future use of these devices for digital applications in circuits and systems are of important strategic decisions in semiconductor industry. In this project, we aimed to grant a significant advantage to European electronic industry by providing fundamental clues for right decisions.
Another part of the Perseus project was related to parallel and distributed computing and to the portability of simulation codes to new computational infrastructures. For that reason, we
analysed the efficiency of numerical methods used in the resolution of the systems of equations arising in the context of semiconductor device simulations when using the finite element method. Moreover, we took into consideration that the variability studies require a large number of computational resources. For that reason, our simulation codes were ported to several computational infrastructures that belong to Swansea University (United Kingdom), to the University of Santiago de Compostela (Spain) and to the Galician Supercomputing Centre (Spain).
The primary beneficiaries of this research are both semiconductor industry and academia. Both of these communities have a huge interest in the further development of electronic technologies even from, perhaps, different reasons. The main interest of semiconductor industry is the aim to lower cost of the production, improve efficiency and offer devices with a greater resistance to variability than competitors, all of these in order to increase the profit. Therefore, the European industry related to semiconductor devices will definitely profit in many ways from the outcome of this research. Likewise, not only the direct producers of semiconductor chips in Europe will profit, the most important impact will be on fabless designer houses where European companies are leading at the world market. The outcomes of this project may provide them with a large advantage, giving them clues of how the next generation of technology will perform. This information is essential for chips and systems designers to keep or even enlarge their positions on the market. The benefit to the European and international academia is even more widespread as the outcome of this research proposal sheds light on the viability of novel transistors for future digital applications.
During the Perseus project, we investigated the performance and scalability of Si and In0.53Ga0.47As silicon/InGaAs-on-insulator vertical fin field effect transistors (SOI FinFETs) using state-of-the-art in-house-built 3D simulation tools: i) drift-diffusion, ii) Monte Carlo (MC) and iii) Non-Equilibrium Green's Function (NEGF) techniques. Three different technological nodes were analysed, with gate lengths of 14.0 12.8 and 10.4 nm for the InGaAs FinFETs and 12.8 10.7 and 8.1 nm for the Si devices. All the device dimensions were designed to meet the 2012 ITRS targets for high-performance logic multi-gate devices. At a high drain bias (0.6 V - 0.7 V), for the Si FinFET, the scaling from the 12.8 nm to 10.7 and 8.1 nm gate lengths increased the on current 25% and 64%, respectively. For the InGaAs FinFET, the increases were 5% and 44% when scaled from 14.0 nm to 12.8 and 10.4 nm gate lengths. Comparing both technologies, the 12.8 and 10.4 nm InGaAs FinFETs delivered 27% and 33% larger on-currents than the 12.8 and 10.7 nm Si FinFETs. The ION/IOFF ratio for the InGaAs FinFETs (9.5-6.6x104) was slightly better than for the Si devices (5.9-6.1x104). The more pronounced S/D tunnelling affecting the InGaAs FinFETs leads to a larger deterioration in their sub-threshold slope (less than 10%) and DIBL (around 20%) when compared to the equivalent gate length Si devices.
Another important part of the project was to study microscopic sources of fluctuations affecting Si and III-V FinFETs. Initially, we studied the impact that three different sources of variability had on the performance of a 14 nm gate length In0.53Ga0.47As FinFET. Low (0.05 V) and high (0.6 V – 0.7 V) drain biases studies were carried out analysing: i) the presence of random dopants in both the channel and the source and drain regions, ii) the line-edge roughness, characterized by the root mean square height (RMS) and the correlation length (CL) and iii) the metal-gate work function variations characterized by the grain size (GS). The study of each source of variability required the simulation of 300 microscopically different transistors. These studies were performed with a 3D parallel finite-element drift-diffusion device simulator that incorporated quantum corrections via a finite-element density gradient approach. The random-dopant induced threshold-voltage (VT) variations (σ VT = 6mV) were similar to those observed in SOI FinFETs. The line-edge roughness induced VT variations (σ VT < 6mV) were similar to the random-dopant ones when RMS=1, and smaller to those observed in SOI FinFETs (around 18 mV). For larger RMS values, the line-edge roughness variability exhibited σ VT ranging from 11 mV, when CL= 10nm and RMS = 2nm, to 19 mV, when CL= 20nm and RMS = 3nm. The metal gate work-function variations were the dominant source of variability in the sub-threshold characteristics. Taking into account that the metal used in the gate was WN, the σ VT ranged from 106 mV when GS = 10 nm to 43 mV when GS = 3 nm, which was larger than the values observed in equivalent TiN metal-gate Si FinFETs.
We also studied and compared the line-edge roughness and TiN metal grain work-function induced variability affecting off and on device characteristics of an In0.53Ga0.47As FinFET with a gate length of 10.4 nm and a Si FinFET with a gate length of 10.7 nm. We analysed the impact of the variability by assessing five figures of merit: threshold voltage (VT), Sub-threshold slope (SS), off-current (IOFF), drain-induced-barrier-lowering (DIBL) and on-current (ION). For this particular study, we have used 3D finite-element quantum-corrected drift-diffusion simulations were employed for variability studies in the sub-threshold region while, in the on-region, we used 3D finite-element quantum-corrected ensemble Monte Carlo simulations. We observed that the In0.53Ga0.47As FinFET was more resilient to the line-edge roughness and metal grain work-function variability in the sub-threshold compared to the Si FinFET due to the stronger carrier confinement present in the In0.53Ga0.47As channel. However, the on-current variability due to line-edge roughness was between 2-3 times larger for the InGaAs FinFET than for the Si device. The on-current variability due to metal gate work-function fluctuations was around 4 times larger for the InGaAs FinFET than for the Si device. For the Si FinFET, both sources of variability had a similar impact on the on-current. However, for the InGaAs FinFET, the on-current metal gate work-function variability was generally much larger than the observed due to line-edge roughness.
The kind of scaling and variability studies performed in the Perseus project for Si and III-V nano-scaled FinEFTs are vital for the proper assessment of their scaling potential. The future use of these devices for digital applications in circuits and systems are of important strategic decisions in semiconductor industry. In this project, we aimed to grant a significant advantage to European electronic industry by providing fundamental clues for right decisions.
Another part of the Perseus project was related to parallel and distributed computing and to the portability of simulation codes to new computational infrastructures. For that reason, we
analysed the efficiency of numerical methods used in the resolution of the systems of equations arising in the context of semiconductor device simulations when using the finite element method. Moreover, we took into consideration that the variability studies require a large number of computational resources. For that reason, our simulation codes were ported to several computational infrastructures that belong to Swansea University (United Kingdom), to the University of Santiago de Compostela (Spain) and to the Galician Supercomputing Centre (Spain).
The primary beneficiaries of this research are both semiconductor industry and academia. Both of these communities have a huge interest in the further development of electronic technologies even from, perhaps, different reasons. The main interest of semiconductor industry is the aim to lower cost of the production, improve efficiency and offer devices with a greater resistance to variability than competitors, all of these in order to increase the profit. Therefore, the European industry related to semiconductor devices will definitely profit in many ways from the outcome of this research. Likewise, not only the direct producers of semiconductor chips in Europe will profit, the most important impact will be on fabless designer houses where European companies are leading at the world market. The outcomes of this project may provide them with a large advantage, giving them clues of how the next generation of technology will perform. This information is essential for chips and systems designers to keep or even enlarge their positions on the market. The benefit to the European and international academia is even more widespread as the outcome of this research proposal sheds light on the viability of novel transistors for future digital applications.