Integrated Modelling, Fault Management, Verification and Reliable Design Environment for Cyber-Physical Systems

CORDIS oferuje możliwość skorzystania z odnośników do publicznie dostępnych publikacji i rezultatów projektów realizowanych w ramach programów ramowych HORYZONT.

Odnośniki do rezultatów i publikacji związanych z poszczególnymi projektami 7PR, a także odnośniki do niektórych konkretnych kategorii wyników, takich jak zbiory danych i oprogramowanie, są dynamicznie pobierane z systemu OpenAIRE .

Rezultaty

Online fault detection mechanisms

Report

Integrated demonstrator on modelling, verification and reliability analysis

Report

System-level reliability analysis tools

Report

FDIR schemes (incl. reconfiguration, health map, fault classification)

Report

Dynamic, semi-formal and formal reliability analysis tools

report

Fault management infrastructure verification tools

Report

Market analysis

Report

Status on fault management

Report

Verification, debugging and testing tools

Report

Dissemination and communication report

Report

Status on modelling, fault/reconfiguration modelling and reliability metrics
Cross-layer CPS modelling framework

Report

Reconfiguration modelling

Report

CPS run-time for SW task deployment

Report

Dynamic, semi-formal and formal reliability analysis methods

Report

Fault models and reliability metrics

Report

Verification, debugging and testing methods

Report

Silicon demonstrator for fault management and mixed-signal reliability verification

Demonstrator

Integrated FPGA demonstrator of the fault management framework

Demonstrator

IMMORTAL Website and factsheet

Website

Publikacje

Gate-level modelling of NBTI-induced delays under process variations

Autorzy: Thiago Copetti, Guilherme Medeiros, Leticia Bolzani Poehls, Fabian Vargas, Sergei Kostin, Maksim Jenihhin, Jaan Raik, Raimund Ubar
Opublikowane w: 2016 17th Latin-American Test Symposium (LATS), 2016, Strona(/y) 75-80, ISBN 978-1-5090-1331-9
Wydawca: IEEE
DOI: 10.1109/LATW.2016.7483343

A Synthesis-Agnostic Behavioral Fault Model for High Gate-Level Fault Coverage

Autorzy: Anton Karputkin, Jaan Raik
Opublikowane w: Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2016, Strona(/y) 1124-1127, ISBN 978-3-9815370-7-9
Wydawca: Research Publishing Services
DOI: 10.3850/9783981537079_0260

Counterexample-guided diagnosis

Autorzy: Heinz Riener, Goerschwin Fey
Opublikowane w: 2016 1st IEEE International Verification and Security Workshop (IVSW), 2016, Strona(/y) 1-6, ISBN 978-1-5090-1141-4
Wydawca: IEEE
DOI: 10.1109/IVSW.2016.7566605

Applying IJTAG-compatible embedded instruments for lifetime enhancement of analog front-ends of cyber-physical systems

Autorzy: Hans G. Kerkhoff, Ghazanfar Ali, Jinbo Wan, Ahmed Ibrahim, Jerrin Pathrose
Opublikowane w: 2017 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), 2017, Strona(/y) 1-6, ISBN 978-1-5386-2880-5
Wydawca: IEEE
DOI: 10.1109/VLSI-SoC.2017.8203464

An automotive MP-SoC featuring an advanced embedded instrument infrastructure for high dependability

Autorzy: Hans G. Kerkhoff, Ghazanfar Ali, Hassan Ebrahimi, Ahmed Ibrahim
Opublikowane w: 2017 International Test Conference in Asia (ITC-Asia), 2017, Strona(/y) 65-70, ISBN 978-1-5386-3051-8
Wydawca: IEEE
DOI: 10.1109/ITC-ASIA.2017.8097113

A dependable AMR sensor system for automotive applications

Autorzy: Andreina Zambrano, Hans G. Kerkhoff
Opublikowane w: 2017 International Test Conference in Asia (ITC-Asia), 2017, Strona(/y) 59-64, ISBN 978-1-5386-3051-8
Wydawca: IEEE
DOI: 10.1109/ITC-ASIA.2017.8097112

Structured scan patterns retargeting for dynamic instruments access

Autorzy: Ahmed Ibrahim, Hans G. Kerkhoff
Opublikowane w: 2017 IEEE 35th VLSI Test Symposium (VTS), 2017, Strona(/y) 1-6, ISBN 978-1-5090-4482-5
Wydawca: IEEE
DOI: 10.1109/VTS.2017.7928955

A cost-efficient dependability management framework for self-aware system-on-chips based on IEEE 1687

Autorzy: Ahmed Ibrahim, Hans G. Kerkhoff
Opublikowane w: 2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS), 2017, Strona(/y) 1-2, ISBN 978-1-5386-0352-9
Wydawca: IEEE
DOI: 10.1109/IOLTS.2017.8046166

Multi-fragment Markov model guided online test generation for MPSoC

Autorzy: Vain, Jüri; Tsiopoulos, Leonidas; Kharchenko, Vyacheslav; Kaur, Apneet; Jenihhin, Maksim; Raik, Jaan
Opublikowane w: 2017
Wydawca: ICT in Education, Research and Industrial Applications

High-level test generation for processing elements in many-core systems

Autorzy: Adeboye Stephen Oyeniran, Raimund Ubar, Siavoosh Payandeh Azad, Jaan Raik
Opublikowane w: 2017 12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), 2017, Strona(/y) 1-8, ISBN 978-1-5386-3344-1
Wydawca: IEEE
DOI: 10.1109/ReCoSoC.2017.8016156

Fault-resilient NoC router with transparent resource allocation

Autorzy: Tsotne Putkaradze, Siavoosh Payandeh Azad, Behrad Niazmand, Jaan Raik, Gert Jervan
Opublikowane w: 2017 12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), 2017, Strona(/y) 1-8, ISBN 978-1-5386-3344-1
Wydawca: IEEE
DOI: 10.1109/ReCoSoC.2017.8016161

Run-time reconfigurable instruments for advanced board-level testing

Autorzy: Igor Aleksejev, Artur Jutman, Sergei Devadze
Opublikowane w: 2016 IEEE AUTOTESTCON, 2016, Strona(/y) 1-8, ISBN 978-1-5090-0790-5
Wydawca: IEEE
DOI: 10.1109/AUTEST.2016.7589627

Embedded instrumentation toolbox for screening marginal defects and outliers for production

Autorzy: Sergei Odintsov, Artur Jutman, Sergei Devadze, Igor Aleksejev
Opublikowane w: 2017 IEEE AUTOTESTCON, 2017, Strona(/y) 1-9, ISBN 978-1-5090-4922-6
Wydawca: IEEE
DOI: 10.1109/AUTEST.2017.8080516

Marginal PCB assembly defect detection on DDR3/4 memory bus

Autorzy: Sergei Odintsov, Artur Jutman, Sergei Devadze
Opublikowane w: 2017 IEEE International Test Conference (ITC), 2017, Strona(/y) 1-10, ISBN 978-1-5386-3413-4
Wydawca: IEEE
DOI: 10.1109/TEST.2017.8242070

Synthesis of Admissible Shield

Autorzy: Laura Humphrey, Bettina Könighofer, Robert Könighofer, Ufuk Topcu
Opublikowane w: 2017, Strona(/y) 134-151
Wydawca: Springer International Publishing
DOI: 10.1007/978-3-319-49052-6_9

Towards Making Fault Injection on Abstract Models a More Accurate Tool for Predicting RT-Level Effects

Autorzy: Tino Flenker, Jan Malburg, Gorschwin Fey, Serhiy Avramenko, Massimo Violante, Matteo Sonza Reorda
Opublikowane w: 2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2017, Strona(/y) 533-538, ISBN 978-1-5090-6762-6
Wydawca: IEEE
DOI: 10.1109/ISVLSI.2017.99

Formal Verification of Masked Hardware Implementations in the Presence of Glitches

Autorzy: Roderick Bloem, Hannes Gross, Rinat Iusupov, Bettina Konighofer, Stefan Mangard, and Johannes Winter
Opublikowane w: 2018
Wydawca: EUROCRYPT

Intermittent Resistance Fault Detection at Board Level

Autorzy: H. Ebrahimi and H.G. Kerkhoff
Opublikowane w: 2018
Wydawca: DDECS

On-Chip Lifetime Prediction for Dependable Many-Processor SoCs based on Slack-Delay and IDDX Data Fusion

Autorzy: G. Ali, J. Pathrose, Y. Zhao and H.G. Kerkhoff
Opublikowane w: 2018
Wydawca: submitted to International Test Conference Asia (ITC-Asia)

IJTAG Compatible Analogue Embedded Instruments for MPSoC Life-time Prediction

Autorzy: J.Pathrose, G.Ali, and H. G. Kerkhoff
Opublikowane w: 2018
Wydawca: 2018 19th IEEE Latin American Test Symposium (LATS)

Mining Latency Guarantees for RTL Designs

Autorzy: Malburg, Jan and Riener, Heinz and Fey, Görschwin
Opublikowane w: 2018
Wydawca: IEEE International Symposium on Multiple-Valued Logic

SMT-Based CPS Parameter Synthesis

Autorzy: Heinz Riener, Robert Könighofer, Görschwin Fey, and Roderick Bloem (DLR, TU Graz)
Opublikowane w: Applied Verification for Continuous and Hybrid Systems, 2016
Wydawca: ARCH'16

Synchronization, Calibration and Triggering of IEEE 1687 Embedded Instruments

Autorzy: A. Jutman, S. Devadze, K. Shibin (Testonica Lab)
Opublikowane w: 2016, Strona(/y) 1-6
Wydawca: WRTLT’2016

Accessing on-chip temperature health monitors using the IEEE 1687 standard

Autorzy: Ali, G. and Badawy, A. and Kerkhoff, H.G. (U.Twente)
Opublikowane w: 2016, Strona(/y) 776-779
Wydawca: IEEE Circuits & Systems Society

A genetic algorithm based remaining lifetime prediction for a VLIW processor employing path delay and IDDX testing

Autorzy: Zhao, Yong and Kerkhoff, H.G. (U.Twente)
Opublikowane w: 2016, Strona(/y) 10-14
Wydawca: IEEE Computer Society

Gate-Level Modelling of NBTI-Induced Delays Under Process Variations

Autorzy: Copetti, Thiago; Medeiros, Guilherme; Poehls, Leticia; Vargas, Fabian; Kostin, Sergei; Jenihhin, Maksim; Raik, Jaan (Tallinn UT)
Opublikowane w: 2016, Strona(/y) 75-80
Wydawca: IEEE Computer Society Press

Counterexample-Guided Diagnosis

Autorzy: Heinz Riener and Goerschwin Fey (DLR)
Opublikowane w: 2016
Wydawca: IVSW

Synthesizing adaptive test strategies from temporal logic specifications

Autorzy: Roderick Bloem, Robert Konighofer, Ingo Pill, Franz Rock
Opublikowane w: 2016 Formal Methods in Computer-Aided Design (FMCAD), 2016, Strona(/y) 17-24, ISBN 978-0-9835678-6-8
Wydawca: IEEE
DOI: 10.1109/FMCAD.2016.7886656

SoCDep²: A framework for dependable task deployment on many-core systems under mixed-criticality constraints

Autorzy: Siavoosh Payandeh Azad, Behrad Niazmand, Peeter Ellervee, Jaan Raik, Gert Jervan, Thomas Hollstein (Tallinn UT)
Opublikowane w: 2016
Wydawca: ReCoSoC

Logic-based implementation of fault-tolerant routing in 3D network-on-chips

Autorzy: Behrad Niazmand, Siavoosh Payandeh Azad, Jose Flich, Jaan Raik, Gert Jervan, Thomas Hollstein
Opublikowane w: 2016 Tenth IEEE/ACM International Symposium on Networks-on-Chip (NOCS), 2016, Strona(/y) 1-8, ISBN 978-1-4673-9030-9
Wydawca: IEEE
DOI: 10.1109/NOCS.2016.7579317

Holistic Approach for Fault-Tolerant Network-on-Chip based Many-Core Systems

Autorzy: Siavoosh Payandeh Azad, Behrad Niazmand, Jaan Raik, Gert Jervan, Thomas Hollstein (Tallinn UT)
Opublikowane w: 2016
Wydawca: DREAMCloud

Online digital compensation Method for AMR sensors

Autorzy: Andreina Zambrano, Hans G. Kerkhoff
Opublikowane w: 2016 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), 2016, Strona(/y) 1-6, ISBN 978-1-5090-3561-8
Wydawca: IEEE
DOI: 10.1109/VLSI-SoC.2016.7753579

Determination of the drift of the maximum angle error in AMR sensors due to aging

Autorzy: Andreina Zambrano, Hans G. Kerkhoff
Opublikowane w: 2016 IEEE 21st International Mixed-Signal Testing Workshop (IMSTW), 2016, Strona(/y) 1-5, ISBN 978-1-5090-2751-4
Wydawca: IEEE
DOI: 10.1109/IMS3TW.2016.7524234

WCET overapproximation for software in the context of a Cyber-Physical System

Autorzy: Niklas Krafczyk, Heinz Riener, Goerschwin Fey
Opublikowane w: 2016 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), 2016, Strona(/y) 1-6, ISBN 978-1-5090-3561-8
Wydawca: IEEE
DOI: 10.1109/VLSI-SoC.2016.7753559

Exact diagnosis using boolean satisfiability

Autorzy: Heinz Riener, Goerschwin Fey
Opublikowane w: Proceedings of the 35th International Conference on Computer-Aided Design - ICCAD '16, 2016, Strona(/y) 1-8, ISBN 9781-450344661
Wydawca: ACM Press
DOI: 10.1145/2966986.2967036

Multilevel design understanding - from specification to logic invited paper

Autorzy: Sandip Ray, Ian G. Harris, Goerschwin Fey, Mathias Soeken
Opublikowane w: Proceedings of the 35th International Conference on Computer-Aided Design - ICCAD '16, 2016, Strona(/y) 1-6, ISBN 9781-450344661
Wydawca: ACM Press
DOI: 10.1145/2966986.2980093

Towards an automated and reusable in-field self-test solution for MPSoCs

Autorzy: Ahmed Ibrahim, Hans G. Kerkhoff
Opublikowane w: 2016 28th International Conference on Microelectronics (ICM), 2016, Strona(/y) 249-252, ISBN 978-1-5090-5721-4
Wydawca: IEEE
DOI: 10.1109/ICM.2016.7847862

Efficient utilization of hierarchical iJTAG networks for interrupts management

Autorzy: Ahmed Ibrahim, Hans G. Kerkhoff
Opublikowane w: 2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2016, Strona(/y) 97-102, ISBN 978-1-5090-3623-3
Wydawca: IEEE
DOI: 10.1109/DFT.2016.7684077

Analysis and design of an on-chip retargeting engine for IEEE 1687 networks

Autorzy: Ahmed Ibrahim, Hans G. Kerkhoff
Opublikowane w: 2016 21th IEEE European Test Symposium (ETS), 2016, Strona(/y) 1-6, ISBN 978-1-4673-9659-2
Wydawca: IEEE
DOI: 10.1109/ETS.2016.7519301

Thermal issues in test: An overview of the significant aspects and industrial practice

Autorzy: J. Alt, P. Bernardi, A. Bosio, R. Cantoro, H. Kerkhoff, A. Leininger, W. Molzer, A. Motta, C. Pacha, A. Pagani, A. Rohani, R. Strasser
Opublikowane w: 2016 IEEE 34th VLSI Test Symposium (VTS), 2016, Strona(/y) 1-4, ISBN 978-1-4673-8454-4
Wydawca: IEEE
DOI: 10.1109/VTS.2016.7477278

Designing reliable cyber-physical systems overview associated to the special session at FDL'16

Autorzy: Gadi Aleksandrowicz, Eli Arbel, Roderick Bloem, Timon Ter Braak, Sergei Devadze, Goerschwin Fey, Maksim Jenihhin, Artur Jutman, Hans G. Kerkhoff, Robert Konighofer, Jan Malburg, Shiri Moran, Jaan Raik, Gerard Rauwerda, Heinz Riener, Franz Rock, Konstantin Shibin, Kim Sunesen, Jinbo Wan, Yong Zhao
Opublikowane w: 2016 Forum on Specification and Design Languages (FDL), 2016, Strona(/y) 1-8, ISBN 979-10-92279-17-7
Wydawca: IEEE
DOI: 10.1109/FDL.2016.7880382

Mining Latency Guarantees for RT-level Designs

Autorzy: Jan Malburg, Heinz Riener, Goerschwin Fey (DLR)
Opublikowane w: 2017
Wydawca: DUHDe

Computing Exact Fault Candidates Incrementally

Autorzy: Heinz Riener and Goerschwin Fey (DLR)
Opublikowane w: 2017
Wydawca: DUHDe

Mapping Abstract and Concrete Hardware Models for Design Understanding

Autorzy: Tino Flenker and Goerschwin Fey (DLR)
Opublikowane w: 2017
Wydawca: DDECS

Counterexample-Guided EF Synthesis of Boolean Functions

Autorzy: Heinz Riener, Ruediger Ehlers, and Goerschwin Fey (DLR)
Opublikowane w: 2017
Wydawca: MBMV

Comprehensive Performance and Robustness Analysis of 2D Turn Models for Network-on-Chips

Autorzy: Siavoosh Payandeh Azad, Behrad Niazmand, Karl Janson, Thilo Kogge, Jaan Raik, Gert Jervan, Thomas Hollstein (Tallinn UT)
Opublikowane w: 2017
Wydawca: ISCAS

Automated Area and Coverage Optimization of Minimal Latency Checkers

Autorzy: Siavoosh Payandeh Azad, Behrad Niazmand, Apneet Kaur Sandhu, Jaan Raik, Gert Jervan, Thomas Hollstein (Tallinn UT)
Opublikowane w: 2017
Wydawca: IEEE

From Online Fault Detection to Fault Management in NoC Routers: A Ground-up Approach

Autorzy: Siavoosh Payandeh Azad, Behrad Niazmand, Karl Janson, Nevin George, Adeboye Stephen Oyeniran, Tsotne Putkaradze, Apneet Kaur, Jaan Raik, Gert Jervan, Raimund Ubar, Thomas Hollstein (Tallinn UT)
Opublikowane w: 2017
Wydawca: DDECS

CEGAR-based EF Synthesis of Boolean Functions with an Application to Circuit Rectification

Autorzy: Heinz Riener, Rüdiger Ehlers, Görschwin Fey (DLR)
Opublikowane w: 2017
Wydawca: ASP-DAC’17

Property Mining using Dynamic Dependency Graphs

Autorzy: Jan Malburg, Tino Flenker, Görschwin Fey (DLR)
Opublikowane w: 2017
Wydawca: ASP-DAC
DOI: 10.1109/ASPDAC.2017.7858327

Synthesizing cooperative reactive mission plans

Autorzy: Rudiger Ehlers, Robert Konighofer, Roderick Bloem
Opublikowane w: 2015 IEEE/RSJ International Conference on Intelligent Robots and Systems (IROS), 2015, Strona(/y) 3478-3485, ISBN 978-1-4799-9994-1
Wydawca: IEEE
DOI: 10.1109/IROS.2015.7353862

Immortalizing many-core systems early experiences of the horizon 2020 action IMMORTAL

Autorzy: Jaan Raik
Opublikowane w: 2015 International Conference on High Performance Computing & Simulation (HPCS), 2015, Strona(/y) 561-562, ISBN 978-1-4673-7813-0
Wydawca: IEEE
DOI: 10.1109/HPCSim.2015.7237092

On-line Fault Classification and Handling in IEEE1687 based Fault Management System for Complex SoCs

Autorzy: K. Shibin, S. Devadze, A. Jutman
Opublikowane w: 2016
Wydawca: IEEE

A hybrid algorithm to conservatively check the robustness of circuits

Autorzy: Niels Thole, Lorena Anghel, and Goerschwin Fey
Opublikowane w: 2016
Wydawca: IEEE

SMT-Based CPS Parameter Synthesis

Autorzy: Heinz Riener, Robert Könighofer, Görschwin Fey, and Roderick Bloem
Opublikowane w: 2016
Wydawca: IEEE

On-line Monitoring of Maximum Angle Error in AMR Sensors

Autorzy: A. Zambrano
Opublikowane w: 2016
Wydawca: IOLTS

Matching abstract and concrete hardware models for design understanding

Autorzy: Tino Flenker and Goerschwin Fey
Opublikowane w: 2016
Wydawca: IEEE

Online Management of Temperature Health Monitors using the IEEE 1687 Standard

Autorzy: G. Ali , A. Badewy and H.G. Kerkhoff
Opublikowane w: 2016
Wydawca: IEEE

A Framework for Comprehensive Automated Evaluation of Concurrent Online Checkers

Autorzy: Pietro Saltarelli, Behrad Niazmand, Jaan Raik, Ranganathan Hariharan, Gert Jervan, Thomas Hollstein
Opublikowane w: 2015 Euromicro Conference on Digital System Design, 2015, Strona(/y) 288-292, ISBN 978-1-4673-8035-5
Wydawca: IEEE
DOI: 10.1109/DSD.2015.15

Automated minimization of concurrent online checkers for Network-on-Chips

Autorzy: Pietro Saltarelli, Behrad Niazmand, Ranganathan Hariharan, Jaan Raik, Gert Jervan, Thomas Hollstein
Opublikowane w: 2015 10th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), 2015, Strona(/y) 1-8, ISBN 978-1-4673-7942-7
Wydawca: IEEE
DOI: 10.1109/ReCoSoC.2015.7238079

A Framework for Combining Concurrent Checking and On-Line Embedded Test for Low-Latency Fault Detection in NoC Routers

Autorzy: Pietro Saltarelli, Behrad Niazmand, Jaan Raik, Vineeth Govind, Thomas Hollstein, Gert Jervan, Ranganathan Hariharan
Opublikowane w: Proceedings of the 9th International Symposium on Networks-on-Chip - NOCS '15, 2015, Strona(/y) 1-8, ISBN 9781-450333962
Wydawca: ACM Press
DOI: 10.1145/2786572.2788713

A Synthesis-Agnostic Behavioral Fault Model for High Gate-Level Fault Coverage

Autorzy: Karputkin, Anton; Raik, Jaan
Opublikowane w: 2016
Wydawca: IEEE

New Fault Models and Self-Test Generation for Microprocessors Using High-Level Decision Diagrams

Autorzy: Artjom Jasnetski, Jaan Raik, Anton Tsertov, Raimund Ubar
Opublikowane w: 2015 IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2015, Strona(/y) 251-254, ISBN 978-1-4799-6780-3
Wydawca: IEEE
DOI: 10.1109/DDECS.2015.56

Identification and Rejuvenation of NBTI-Critical Logic Paths in Nanoscale Circuits

Autorzy: Jenihhin, Maksim; Squillero, Giovanni; Copetti, Thiago Santos; Tihhomirov, Valentin; Kostin, Sergei; Gaudesi, Marco; Vargas, Fabian; Raik, Jaan; Sonza Reorda, Matteo; Bolzani Poehls, Leticia; Ubar, Raimund; Medeiros, Guilherme Cardoso
Opublikowane w: Journal of Electronic Testing-Theory and Applications (JETTA), 2016
Wydawca: SPRINGER

Semi-Formal Methods for Soft Error Analysis

Autorzy: Patrick Klampfl, Robert Könighofer, Roderick Bloem, Ayrat Khalimov, Aiman Abu-Yonis, Shiri Moran
Opublikowane w: 2017
Wydawca: CoRR abs/1712.04291

Designing Reliable Cyber-Physical Systems, Lecture Notes in Electrical Engineering: Languages, Design Methods, and Tools for Electronic System Design

Autorzy: Gadi Aleksandrowicz, Eli Arbel, Roderick Bloem, Timon D. ter Braak, Sergei Devadze, Goerschwin Fey, Maksim Jenihhin, Artur Jutman, Hans G. Kerkhoff, Robert Könighofer, Shlomit Koyfman, Jan Malburg, Shiri Moran, Jaan Raik, Gerard Rauwerda, Heinz Riener, Franz Röck, Konstantin Shibin, Kim Sunesen, Jinbo Wan, Yong Zhao
Opublikowane w: 2018, Strona(/y) 15-38
Wydawca: Springer International Publishing
DOI: 10.1007/978-3-319-62920-9_2

Design and Implementation of a dependable CPSoC for Automotive Applications

Autorzy: G. Ali, H. Ebrahimi, J. Pathrose and H.G. Kerkhoff
Opublikowane w: 2018
Wydawca: submitted to Industrial Cyber-Physical Systems (ICPS)

A Flexible Distributed Simulation Environment for Cyber-Physical Systems Using ZeroMQ

Autorzy: Ofenloch, Annika and Greif, Fabian
Opublikowane w: Journal of Communications, 2018
Wydawca: Journal of Communications

Reliable Health Monitoring and Fault Management Infrastructure based on Embedded Instrumentation and IEEE 1687

Autorzy: A. Jutman, K. Shibin, S. Devadze (Testonica Lab)
Opublikowane w: 2016, Strona(/y) 240-249
Wydawca: AUTOTESTCON’2016

Learning Models of a Network Protocol using Neural Network Language Models

Autorzy: Bernhard Aichernig, Roderick Bloem, Franz Pernkopf, Franz Röck, Tobias Schrank and Martin Tappler (TU Graz)
Opublikowane w: 2016
Wydawca: IEEE Symposium on Security and Privacy

Killing strategies for model-based mutation testing

Autorzy: Bernhard K. Aichernig, Harald Brandl, Elisabeth Jöbstl, Willibald Krenn, Rupert Schlick, Stefan Tiran
Opublikowane w: Software Testing, Verification and Reliability, Numer 25/8, 2015, Strona(/y) 716-748, ISSN 0960-0833
Wydawca: John Wiley & Sons Inc.
DOI: 10.1002/stvr.1522

Health Management for Self-Aware SoCs Based on IEEE 1687 Infrastructure

Autorzy: Konstantin Shibin, Sergei Devadze, Artur Jutman, Martin Grabmann, Robin Pricken
Opublikowane w: IEEE Design & Test, Numer 34/6, 2017, Strona(/y) 27-35, ISSN 2168-2356
Wydawca: IEEE Computer Society
DOI: 10.1109/MDAT.2017.2750902

Identification and Rejuvenation of NBTI-Critical Logic Paths in Nanoscale Circuits

Autorzy: Maksim Jenihhin, Giovanni Squillero, Thiago Santos Copetti, Valentin Tihhomirov, Sergei Kostin, Marco Gaudesi, Fabian Vargas, Jaan Raik, Matteo Sonza Reorda, Leticia Bolzani Poehls, Raimund Ubar, Guilherme Cardoso Medeiros
Opublikowane w: Journal of Electronic Testing, Numer 32/3, 2016, Strona(/y) 273-289, ISSN 0923-8174
Wydawca: Kluwer Academic Publishers
DOI: 10.1007/s10836-016-5589-x

metaSMT: focus on your application and not on solver integration

Autorzy: Heinz Riener, Finn Haedicke, Stefan Frehse, Mathias Soeken, Daniel Große, Rolf Drechsler, Goerschwin Fey
Opublikowane w: International Journal on Software Tools for Technology Transfer, 2016, ISSN 1433-2779
Wydawca: Springer Verlag
DOI: 10.1007/s10009-016-0426-1

Debugging hardware designs using dynamic dependency graphs

Autorzy: Jan Malburg, Alexander Finder, Görschwin Fey (DLR)
Opublikowane w: Journal of Microprocessors and Microsystems: Embedded Hardware Design (MICPRO), 2016, ISSN 0141-9331
Wydawca: Elsevier BV

Simulating NBTI Degradation in Arbitrary Stressed Analog/Mixed-Signal Environments

Autorzy: Jinbo Wan, Hans Kerkhoff, Jaap Bisschop
Opublikowane w: IEEE Transactions on Nanotechnology, 2016, Strona(/y) 1-1, ISSN 1536-125X
Wydawca: Institute of Electrical and Electronics Engineers
DOI: 10.1109/TNANO.2015.2505092

Energy Efficient Multi-Fragment Markov Model Guided Online Model-Based Testing for MPSoC

Autorzy: Vain,Jüri; Tsiopoulos, Leonidas; Kharchenko, Vyacheslav; Kaur, Apneet; Jenihhin, Maksim; Raik, Jaan; Nõmm Sven
Opublikowane w: Green-IT Engineering: Social, Business and Industrial Applications (1−21), 2018
Wydawca: Springer

Cooperative Reactive Synthesis

Autorzy: Roderick Bloem, Rüdiger Ehlers, Robert Könighofer
Opublikowane w: Automated Technology for Verification and Analysis, 2015, Strona(/y) 394-410, ISBN 978-3-319-24953-7
Wydawca: Springer International Publishing
DOI: 10.1007/978-3-319-24953-7_29

Case Study: Automatic Test Case Generation for a Secure Cache Implementation

Autorzy: Roderick Bloem, Daniel Hein, Franz Röck, Richard Schumi
Opublikowane w: Tests and Proofs, 2015, Strona(/y) 58-75, ISBN 978-3-319-21215-9
Wydawca: Springer International Publishing
DOI: 10.1007/978-3-319-21215-9_4

Prawa własności intelektualnej

ASSURING CHIP RELIABILITY WITH AUTOMATIC GENERATION OF DRIVERS AND ASSERTIONS

Numer wniosku/publikacji: US 9483591
Data: 2015-11-27
Wnioskodawca/wnioskodawcy: IBM ISRAEL - SCIENCE AND TECHNOLOGY LTD

Wyszukiwanie danych OpenAIRE...

Rezultaty

Publikacje

Prawa własności intelektualnej

Udostępnij tę stronę Udostępnij tę stronę w mediach społecznościowych

Pobierz Pobierz zawartość strony