Descrizione del progetto
Nuovo piano di comunicazione wireless su chip
I futuri sistemi di comunicazione wireless e le piattaforme di calcolo devono offrire velocità di trasmissione dati molto più elevate, maggiore flessibilità e un’efficienza energetica significativamente più alta rispetto ai sistemi attuali. Poiché sono ampiamente disponibili processori eterogenei, sono necessarie nuove piattaforme per sfruttare l’enorme quantità di potenza di calcolo. Per garantire un livello di efficienza quasi prossimo all’efficienza ASIC (application-specific integrated circuit, circuito integrato per applicazioni specifiche) senza costi, tempi di sviluppo o limitazioni, il progetto WiPLASH, finanziato dall’UE, sta sviluppando un piano di comunicazione wireless su chip per fornire plasticità architetturale, riconfigurabilità e adattamento per qualsiasi esigenza applicativa, senza alcuna perdita di generalità. In particolare, il progetto studierà un prototipo di antenna in grafene miniaturizzato e sintonizzabile nella banda terahertz. Inoltre, integrerà componenti RF in grafene con ricetrasmettitori a onde submillimetriche e metterà alla prova reti wireless a bassa potenza riconfigurabili a scala di chip.
Obiettivo
The main design principles in computer architecture have shifted from a monolithic scaling-driven approach towards an emergence of heterogeneous architectures that tightly co-integrate multiple specialized computing and memory units. This is motivated by the urgent need of very high parallelism and by energy constraints. This heterogeneous hardware specialization requires interconnection mechanisms that integrate the architecture. State-of-the-art approaches are 3D stacking and 2.D architectures complemented with a Network-on-Chip (NoC) to interconnect the components. However, such interconnects are fundamentally monolithic and rigid, and are unable to provide the efficiency and architectural flexibility required by current and future key ICT applications. The main challenge is to introduce diversification and specialization in heterogeneous processor architectures while ensuring their generality and scalability.
In order to achieve this, the WiPLASH project aims to pioneer an on-chip wireless communication plane able to provide architectural plasticity, reconfigurability and adaptation to the application requirements with near-ASIC efficiency but without any loss of generality. For this, the WiPLASH consortium will provide solid experimental foundations of the key enablers of on-chip wireless communication at the functional unit level as well as their technological and architectural integration. The main goals are: (i) prototype a miniaturized and tunable graphene antenna in the terahertz band, (ii) co-integrate graphene RF components with submillimeter-wave transceivers and (iii) demonstrate low-power reconfigurable wireless chip-scale networks. The culminating goal is to demonstrate that the wireless plane offers the plasticity required by future computing platforms by improving at least one key application (mainly biologically-plausible deep learning architectures) by 10X in terms of execution speed and energy-delay product over a state-of-the-art baseline.
Campo scientifico
- engineering and technologynanotechnologynano-materialstwo-dimensional nanostructuresgraphene
- engineering and technologyelectrical engineering, electronic engineering, information engineeringelectronic engineeringanalogue electronics
- natural sciencescomputer and information sciencesartificial intelligencemachine learningdeep learning
- engineering and technologyelectrical engineering, electronic engineering, information engineeringinformation engineeringtelecommunicationsradio technology
Parole chiave
Programma(i)
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Vedi altri progetti per questo bandoBando secondario
H2020-FETOPEN-2018-2019-2020-01
Meccanismo di finanziamento
RIA - Research and Innovation actionCoordinatore
08034 Barcelona
Spagna