ASML concentrated on the integration of large subsystems and the subsequent qualification of the 1st EUV lithographic system for the 7nm node. It has shown to meet all requirements, including the productivity of 125 WpH. Further, ASML finished the feasibility of the Hyper NA EUV system.
DEMCON has realized and tested a new qualification tool for the next generation positioning module. Functionality and performance of the positioning module was demonstrated.
Fraunhofer achieved within one deposition process, reduction of layer roughness, improvement of stress uniformity on flat and strongly curved substrate surfaces, extension of mask deposition technique for fabrication of free-form thickness profiles to substrates with up to 300 mm diameter. This enables the manufacturing of high reflective, low stray light and low intrinsic stress coatings for Hyper NA EUV mirrors.
A complete process line to manufacture X-large DOE’s is installed at IMS and 17” DOE demonstrators are processed.
VDL-ETG has supported the integration and qualification of EUV source systems.
Zeiss continued the development of the technological basis for the Hyper NA EUV projection lens. The concept for the production of the oversized mirrors was created and the concept for the measurement of aspherical mirrors was successfully evaluated. The deposition technology for multilayer reflection surfaces was developed.
During the project time span, the metrology partners developed and qualified metrology tools and modules for the 7nm node. Samples from the imec’s pilot line were distributed to the partners for process characterization.
AMIL developed and qualified a next generation optical wafer inspection and an E-beam inspection and review tool.
The T800 next generation OCD tool from Nova includes a new information channel which add new applications to the T600MMSR current state of the art.
Integrated overlay by KTI saves a precious FAB real estate and therefore improves the overlay metrology cost of ownership.
FEI completed CDSEM application development for high resolution imaging of 7nm gate layer and next generation FIB/SEM and near line TEM EDS developments with 7nm qualifications.
New process steps are developed by Applied Materials, ASM and Lan Research enabling 7nm technology by using innovative process upgrades of different platforms either installed at imec or at supplier sites. The development of new processes includes multi-patterning schemes and different process options for BEOL and FEOL.
An extensive material optimization was conducted to single out an alternative EUV mask absorber to mitigate M3D effects, while fulfilling mask requirements. Most interesting materials from lithographic perspective pose extreme challenges on the current technology of subtractive patterning (etching) and of e-beam repair.
The work on alternative candidate membrane films resulted in several solutions, e.g. carbon nanotubes. For baseline pSi-based membranes developed by ASML, a first commercial supplier for pellicles is available. The commercial pellicle shows good results on CD and EUV power performance.
Fraunhofer IISB completed the search into attenuated EUV phase shift materials using imaging simulations and the experimental verification was included.
Developing the mask maintenance infrastructure by SUSS has started on the MaskTrackPro and a test has been executed demonstrating the compatibility of its handling with of a reticle with pellicle.
From the patterning options validation based on the 193i-multi patterning vs single exposure EUV pattering benchmark for all the critical layers, a final set of design rules was deduced.
The FEOL and MOL process assumptions were validated, and modules were built. All required process steps for the respective modules are developed.
The BEOL patterning options validation was conducted for all critical layers. Process optimizations including benchmarking of different metallization options were performed. The BEOL electrical integration highlighted the process window marginality for hybrid Metal 2 patterning. The latter triggered a mild relaxation of the T2T design rule, paving the path for EUV SE for M2 and M2/V1 dual damascene integration.
Full device integration and electrical characterization was done. In a first electrical lot low-k dielectric spacers were successfully integrated to overcome the capacitance increase caused by the scaled contacted poly pitch for 7nm node technology.
The project resulted in 14 open air publications and 56 project publications, and 33 patents.
